`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10/22/2022 06:24:53 PM
// Design Name: 
// Module Name: test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

function [5:0] calc_pwm (input [5:0] brightness); 
  begin
    calc_pwm = brightness;
  end
endfunction

module led_game(
    input wire clk,
    input wire [5:0] brightness,
    output reg [3:0] leds
    );
    
  reg [15:0] count;
  wire [5:0] pwm0, pwm1, pwm2, pwm3;
  
  assign pwm0 = calc_pwm(brightness);
  assign pwm1 = calc_pwm(brightness+16);
  assign pwm2 = calc_pwm(brightness+24);
  assign pwm3 = calc_pwm(brightness+48);
   
  always @(posedge clk) begin
    count <= count + 1;
  end
  
  always @(pwm0, count) begin
    if (pwm0 <= count[15:10]) begin
      leds[0] <= 1'b0;
    end else begin
      leds[0] <= 1'b1;
    end
  end

  always @(pwm1, count) begin
    if (pwm1 <= count[15:10]) begin
      leds[1] <= 1'b0;
    end else begin
      leds[1] <= 1'b1;
    end
  end
  
  always @(pwm2, count) begin
    if (pwm2 <= count[15:10]) begin
      leds[2] <= 1'b0;
    end else begin
      leds[2] <= 1'b1;
    end
  end
  
  always @(pwm3, count) begin
    if (pwm3 <= count[15:10]) begin
      leds[3] <= 1'b0;
    end else begin
      leds[3] <= 1'b1;
    end
  end
  
      
endmodule
